Homogeneous copper-palladium alloy plating for enhancement of electro-migration resistance in interconnects

ABSTRACT

A method for plating a homogenous copper-palladium alloy. The method includes providing a plating solution to an electrochemical plating cell. The plating solution includes a copper ion source at a concentration of between about 0.1 M and about 1.0 M and a palladium ion source at a concentration of between about 0.0005 M and about 0.1 M. The method further includes supplying an electrical deposition bias to a plating surface. The electrical deposition bias is configured to simultaneously deposit copper ions and palladium ions onto the plating surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. provisional patentapplication serial No. 60/415,593, filed Oct. 2, 2002, which is hereinincorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] Embodiments of the invention generally relate to a method andapparatus for depositing a layer of a metal or metal alloy into a highaspect ratio feature on a semiconductor substrate.

[0004] 2. Description of the Related Art

[0005] Metallization of sub-quarter micron sized features is afoundational technology for present and future generations of integratedcircuit manufacturing processes. More particularly, in devices such asultra large scale integration-type (ULSI) devices, i.e., devices havingintegrated circuits with more than a million logic gates, the multilevelinterconnects that lie at the heart of these devices are generallyformed by filling high aspect ratio interconnect features with aconductive material, such as copper or aluminum, for example.Conventionally, deposition techniques such as chemical vapor deposition(CVD) and physical vapor deposition (PVD), for example, have been usedto fill these interconnect features. However, as interconnect sizesdecrease and aspect ratios increase, void-free interconnect feature fillvia conventional metallization techniques becomes increasinglydifficult. As a result, plating techniques, such as electrochemicalplating (ECP) and electroless plating, have emerged as viable processesfor void free filling of sub-quarter micron sized high aspect ratiointerconnect features in integrated circuit manufacturing processes.

[0006] In an ECP process, for example, sub-quarter micron sized highaspect ratio features formed into the surface of a substrate may beefficiently filled with a conductive material, such as copper. ECPplating processes are generally two stage processes, in which a seedlayer is first formed over the surface features of the substrate, andthen the surface features of the substrate are exposed to an electrolytesolution, while an electrical bias is simultaneously applied between thesubstrate and an anode positioned within the electrolyte solution. Theelectrolyte solution is generally rich in ions to be plated onto thesurface of the substrate, and therefore, the application of theelectrical bias causes these ions to be plated onto the seed layer.

[0007] However, one challenge associated with ECP copper depositionprocesses is that the extremely small size of the conductiveinterconnect lines results in a substantial increase in the potential toform voids in the interconnect lines via electromigration modes.Inasmuch as the substantial increase in the potential to form voids inthe interconnect lines via electromigration modes is directly related tothe intrinsic electromigration (and/or stress migration) resistance ofthe copper line, it is desirable to generate conductive lines havingminimal electrical resistance, while also having desirableelectromigration characteristics. One method for improving theelectromigration (and/or stress migration) resistance of copper lines isto alloy copper with a heavy metal without appreciably increasing theelectrical resistance of the alloy when compared to copper, whilesimultaneously increasing the electromigration resistancecharacteristics of the alloy.

[0008] Palladium has been found to be a suitable alloying element thatimproves the electromigration (and/or stress migration) characteristicof copper plated layers. However, current deposition techniquesgenerally deposit individual layers of copper and palladium on top ofeach other, and then anneal the entire structure to form acopper-palladium alloy. This approach may be problematic, since theannealing process has been shown to form copper-palladium alloys havingvarying uniformity/homogeneity in cross-section that generatesinconsistent conductive characteristics along the conductive lines,which may result in void formation. Additionally, although deposition ofcopper-palladium alloys via electrochemical deposition has beenconventionally used to generate solder bump points and other largerscale features, conventional apparatuses and methods have not beensuccessful in depositing a homogenous copper-palladium alloy into a highaspect ratio feature, i.e., a feature where the height to width ratio isat least 4:1, without encountering voids in the fill deposition.Additionally, conventional copper-palladium alloy plating methods havefocused upon alloys having large percentages of palladium and smallconcentrations of copper, which is undesirable for semiconductor deviceinterconnects, since the electrical resistance characteristics ofpalladium rich alloys are substantially higher than copper or copperrich alloys. Void free fill of high aspect ratio features, such as thosethat make up the multilevel conductive interconnects in semiconductordevices, is critical to the continued success and continued progress ofULSI technology.

[0009] Therefore, a need exists for a method and apparatus fordepositing a substantially homogenous copper-palladium alloy thin filminto a high aspect ratio feature of a semiconductor device.

SUMMARY OF THE INVENTION

[0010] Embodiments of the invention are generally directed to a methodfor plating a homogenous copper-palladium alloy. The method includesproviding a plating solution to an electrochemical plating cell. Theplating solution includes a copper ion source at a concentration ofbetween about 0.1 M and about 1.0 M and a palladium ion source at aconcentration of between about 0.0005 M and about 0.1 M. The methodfurther includes supplying an electrical deposition bias to a platingsurface. The electrical deposition bias is configured to simultaneouslydeposit copper ions and palladium ions onto the plating surface.

[0011] Embodiments of the invention are further directed to a method forelectrochemically plating an alloy onto a semiconductor substrate. Themethod includes providing a plating solution containing copper ions andpalladium ions, immersing a working surface of a substrate and an anodein the plating solution, and applying an electrical plating bias betweenthe anode and the working surface. The electrical plating bias isconfigured to simultaneously plate copper and palladium out of theplating solution and onto the working surface.

[0012] Embodiments of the invention are further directed to a platingsolution for plating a copper palladium alloy. The plating solutionincludes a source of copper ions, a source of palladium ions, an acid ata concentration of between about 5 g/L about 200 g/L, and at least oneplating solution additive configured to control plating characteristics.

[0013] Embodiments of the invention are further directed to anelectrochemical plating cell configured to plate a homogenouscopper-palladium alloy into features of a semiconductor device. Theplating cell includes a substrate support member having a substantiallyplanar lower surface configured to engage a non-production side of asubstrate, an annular insulative cathode contact ring having a pluralityof conductive substrate biasing members formed therein. Each of theplurality of conductive biasing members is configured to electricallyengage a plating surface of a substrate. The plating cell furtherincludes a plating cell container configured to hold a volume ofelectrochemical plating solution comprising a concentration of copperions of between about 0.1 M and about 1.0 M and a concentration ofpalladium ions between about 0.0005 M and about 0.1 M, a power supply inelectrical communication with the plurality of conductive members andbeing configured to apply a plating bias to the plating surface, ananode positioned in the plating cell container in a position where theanode is immersed in the electrochemical plating solution, and a processcontroller programmed to ensure that the copper ion concentration in theplating solution is between about 0.1 M and about 1.0 M and thepalladium ion concentration in the plating solution is between about0.0005 M and about 0.1 M.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] So that the manner in which the above recited features of thepresent invention are attained and can be understood in detail, a moreparticular description of the invention, briefly summarized above, maybe had by reference to the embodiments thereof which are illustrated inthe appended drawings. It is to be noted, however, that the appendeddrawings illustrate only typical embodiments of this invention and aretherefore not to be considered limiting of its scope, for the inventionmay admit to other equally effective embodiments.

[0015]FIG. 1 illustrates an exemplary weir-type plating cell of theinvention.

[0016]FIG. 2 illustrates an exemplary face down type plating cell of theinvention.

[0017]FIG. 3 illustrates a partial sectional perspective view of anexemplary electrochemical plating cell of the invention.

[0018]FIG. 4 illustrates a current versus voltage schematic plot forindividual deposition of copper and palladium.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019]FIG. 1 illustrates a cross sectional view of an exemplaryweir-type plater 100 of the invention. Plater 100 generally includes anelectrolyte container 112 having an open top portion and a substrateholder 114 that is pivotally disposed above the electrolyte container112, which contains an electrolyte solution. The substrate holder 114 isconfigured for immersing a substrate into the electrolyte solution andremoving the substrate from the electrolyte solution. The substrateholder 114 is capable of securing and positioning the substrate in adesired position during processing.

[0020] A contact ring 120 is positioned proximate the lower surface ofthe lid/substrate holder 114, and is in electrical communication with apower supply (not shown). As such, the contact ring 120 is configured toelectrically engage the substrate 122 and provide a plating bias to thesubstrate 122. The contact ring 120, which may be annular in shape,generally includes a plurality of conductive contact pins 126distributed about a peripheral portion of the contact ring 120. Theplurality of contact pins 126 generally extend radially below theperimeter of the substrate 122 such that the tips of the contact pins126 contact a conductive seed layer formed on the substrate 122.Additionally, the electrolyte container 112 may include a separationmembrane 128 positioned between an anode 116 and the substrate 122. Themembrane 128 may operate to define respective anodic and cathodicchambers in the electrolyte container 112, i.e., the anodic chamber willsurround the anode and the cathodic chamber will be adjacent the platingsurface of the substrate. The anode 116 is configured to supply ions toa plating solution contained within container 112. The separationmembrane 128 is generally a membrane configured to allow the platingsolution supplied to the container 112 to flow therethrough, whilerestricting the flow of other materials, i.e., contaminants, copperballs, etc., from flowing through the membrane 128 and contacting thesubstrate 122. The plating solution is supplied to the electrolytecontainer 112 by a supply line 118, which is generally in fluidcommunication with a pump and an electrolyte supply system, as is knownin the art.

[0021] Additionally, the separation membrane 128 may also be configuredto prevent the Pd²⁺ ions from penetrating into the anode chamber. Theanodic chamber may also be configured to have a positive pressure withrespect to the cathodic chamber so that a fluid flow exists only in thedirection towards the cathodic chamber.

[0022] A process controller 190 is connected to the plater 100 forinstructing the plater 100 to perform one or more processing stepsassociated with embodiments of the invention. The process controller 190may include a CPU, which may be any form of computer processors that canbe used in an industrial setting for controlling various chambers andsubprocessors, and a memory for storing information and instructions tobe executed by the CPU.

[0023]FIG. 2 illustrates a cross sectional view of another exemplaryelectroplating process cell 200 of the invention. Process cell 200generally includes a head assembly 210, a process kit 220, and anelectrolyte collector 240. The electrolyte collector 240 is generallyconfigured to be secured onto a mainframe (not shown) of a platingsystem (not shown). The electrolyte collector 240 generally includes aninner wall 246, an outer wall 248, and a bottom 247 connecting therespective walls. An electrolyte outlet 249 is disposed through thebottom 247 of the electrolyte collector 240 and connected to anelectrolyte replenishing system (not shown) through tubes, hoses, pipesor other fluid transfer connectors. The head assembly 210 is generallymounted onto a head assembly frame 252 that includes a mounting post 254and a cantilever arm 256. The mounting post 254 is generally mountedonto a mainframe body 214, and the cantilever arm 256 generally extendslaterally from an upper portion of the mounting post 254. Generally, themounting post 254 provides rotational movement with respect to avertical axis along the mounting post 254 to allow rotation of the headassembly 210. The lower end of the cantilever arm 256 is generallyconnected to a cantilever arm actuator 257, such as a pneumaticcylinder, mounted on the mounting post 254. The cantilever arm actuator257 provides pivotal movement of the cantilever arm 256 with respect tothe joint between the cantilever arm 256 and the mounting post 254.

[0024] The head assembly 210 generally includes a substrate holderassembly 250 and a substrate assembly actuator 258. The substrateassembly actuator 258 operates to rotate and/or raise/lower thesubstrate holder assembly 250. The substrate holder assembly 250generally includes a substrate holder 264 and an integrally formedcathode contact ring 266. The substrate holder assembly 250 includes aplurality of vacuum channels 267 formed in a lower side of the substrateholder assembly 250. The vacuum channels 267, which are generally incommunication with a vacuum pump (not shown), are annularly positionedabout the lower surface of the substrate holder assembly 250 andconfigured to provide sufficient vacuum pressure to secure a substratethereto for processing. The contact ring 266, which is generally inelectrical communication with a power supply (not shown), includes anannular body having a plurality of conducting members disposed thereonfor communicating electrical energy from the power supply to a substratepositioned on the holder assembly 250. The annular body of the contactring 266 is generally constructed of an insulating material in order toelectrically isolate the plurality of conducting members fromsurrounding components other than the substrate. The body and conductingmembers of the contact ring 266 generally form a diametrically interiorsubstrate-seating surface which, during processing, may support thesubstrate being processed by process cell 200. The contact ring 266 isconfigured to electrically engage and contact the substrate beingprocessed on the non-production side of the substrate, i.e., on thebackside of the substrate, so that the production side of the substrateis free of electrical or mechanical contacts therewith. As such,substrates processed in process cell 200 will generally have a backsideconductive layer configured to electrically engage the backside contactring deposited thereon. Additionally, the backside conductive layer,which is generally a seed layer extension, may be configured tocommunicate electrical power applied thereto to the front or productionside of the substrate in order to cause plating thereon.

[0025] A process controller 290 is connected to the process cell 200 forinstructing the process cell 200 to perform one or more processing stepsassociated with embodiments of the invention. The process controller 290may include a CPU, which may be any form of computer processors that canbe used in an industrial setting for controlling various chambers andsubprocessors, and a memory for storing information and instructions tobe executed by the CPU.

[0026]FIG. 3 illustrates a perspective and partial sectional view ofanother exemplary electrochemical plating cell 300 of the invention.Plating cell 300 generally includes an outer basin 301 and an innerbasin 302 positioned within outer basin 301. Inner basin 302 isgenerally configured to contain a plating solution that is used to platea metal, e.g., copper, onto a substrate during an electrochemicalplating process. During the plating process, the plating solution isgenerally continuously supplied to inner basin 302 (at about 1 gallonper minute for a 10-liter plating cell, for example), and therefore, theplating solution continually overflows the uppermost point of innerbasin 302 and runs into outer basin 301. The overflow plating solutionis then collected by outer basin 301 and drained therefrom forrecirculation into basin 302. As illustrated in FIG. 3, plating cell 300is generally positioned at a tilt angle, i.e., the frame portion 303 ofplating cell 300 is generally elevated on one side such that thecomponents of plating cell 300 are tilted between about 3° and about30°. Therefore, in order to contain an adequate depth of platingsolution within inner basin 302 during plating operations, the uppermostportion of basin 302 may be extended upward on one side of plating cell300, such that the uppermost point of inner basin 302 is generallyhorizontal and allows for contiguous overflow of the plating solutionsupplied thereto around the perimeter of basin 302.

[0027] The frame member 303 of plating cell 300 generally includes anannular base member 304 secured to frame member 303. Since frame member303 is elevated on one side, the upper surface of base member 304 isgenerally tilted from the horizontal at an angle that corresponds to theangle of frame member 303 relative to a horizontal position. Base member304 includes an annular or disk shaped recess formed therein, theannular recess being configured to receive a disk shaped anode member305. Base member 304 further includes a plurality of fluid inlets/drains309 positioned on a lower surface thereof. Each of the fluidinlets/drains 309 are generally configured to individually supply ordrain a fluid to or from either the anode compartment or the cathodecompartment of plating cell 300. Anode member 305 generally includes aplurality of slots 307 formed therethrough, wherein the slots 307 aregenerally positioned in parallel orientation with each other across thesurface of the anode 305. The parallel orientation allows for densefluids generated at the anode surface to flow downwardly across theanode surface and into one of the slots 307. Plating cell 300 furtherincludes a membrane support assembly 306. Membrane support assembly 306is generally secured at an outer periphery thereof to base member 304,and includes an interior region 308 configured to allow fluids to passtherethrough via a sequence of oppositely positioned slots and bores.The membrane support assembly may include an o-ring type seal positionednear a perimeter of the membrane, wherein the seal is configured toprevent fluids from traveling from one side of the membrane secured onthe membrane support 306 to the other side of the membrane.

[0028] A process controller 390 is connected to the process cell 300 forinstructing the process cell 300 to perform one or more processing stepsassociated with embodiments of the invention. The process controller 390may include a CPU, which may be any form of computer processors that canbe used in an industrial setting for controlling various chambers andsubprocessors, and a memory for storing information and instructions tobe executed by the CPU.

[0029] In operation, regardless of the plating cell configurationutilized, a substrate to be plated is generally secured to a substratesupport member and the plating surface of the substrate is brought intocontact with a plating solution. While in contact with the platingsolution, an electrical bias is applied to a seed layer deposited on theplating surface of the substrate. The electrical bias is generally abias configured to bias the substrate surface/seed layer with a cathodiccharge, which causes the plating ions in the plating solution to beurged out of the solution and to plate on the cathodically chargedsubstrate surface/seed layer.

[0030] In conventional plating systems, the plating solution generallyincludes an aqueous solution that contains sulfuric acid, phosphoricacid, or derivatives thereof. The electroplating solution may furtherinclude one or more organic additives, i.e., levelers, suppressors,accelerators, and/or other additives known in the art to facilitatecontrol over the plating process. The additives are typically organicmaterials that are known to adsorb onto the surface of the substratebeing plated. Useful suppressors, for example, may include polyethers,such as polyethylene, glycol, or other polymers such as polypropyleneoxide, that are known to inhibit the rate of deposition on thesubstrate. Useful accelerators, for example, may include sulfides ordisulfides, such as bis (3-sulfopropyl) disulfide, which affects themicrostructure of copper deposited on the substrate. Useful levelers maygenerally include amines or polyamines, which improve the thicknessdistribution of copper deposited on the substrate.

[0031] Inasmuch as the present invention is configured to deposit ahomogenous copper-palladium alloy in an electrochemical plating process,conventional copper plating solutions may be modified to include thepalladium ions necessary to support copper-palladium plating. However,the amount of copper and palladium deposited in an electrochemicalplating process is generally governed by two factors: first, the platingpotential at which plating operations are conducted; and second, theconcentration of palladium ions in the plating solution in proportion tothe concentration of the copper ions in the solution. As a result of theresistivity of copper being limited by the concentration of palladiumions, the amount of palladium in the plated alloy may be limited to lessthan about 2 weight percent, preferably, between about 0.2 weightpercent and about 1.5 weight percent. In one embodiment, it is desirableto maintain the palladium percentage in the plated alloy below about 1.5weight percent to provide good conductivity characteristics as well asgood electromigration characteristics when compared to conventionalcopper interconnects. In another embodiment, the plated alloy has about1.5 weight percent of palladium versus about 98.5 weight percent or moreof copper. Additionally, any local agglomeration of palladium, whichresults from high concentrations of palladium in the plating solution orthe copper-palladium alloy generated, will also produce disadvantages.Therefore, embodiments of the invention contemplate calculatedconcentrations of palladium configured to generate optimal platingcharacteristics without forming intermetallics, wherein the calculatedconcentrations of palladium are generally substantially smaller than theconcentrations of the copper in the plating solution.

[0032] With regard to the plating potential used in plating a homogenouscopper-palladium thin film, it is known that specific plating potentialranges result in optimized plating of specific metals. Therefore, inorder for a copper-palladium alloy to be plated from a unitary platingsolution, the plating potential applied during plating operations willgenerally overlap the plating potential ranges for both metals. As such,when the plating potential applied is resident in the plating ranges forboth metals, simultaneous plating of both metals may be conducted. It isto be noted, however, that the plating potential for metals varies withthe concentration of the metal ions in the plating solution, along withother parameters. As such, particular processing parameters will varyfrom processing system to processing system. However, for reference, thestandard reduction potential for copper is 0.34 volts with respect to astandard hydrogen electrode, while the standard reduction potential forpalladium is 0.95 volts with respect to a standard hydrogen electrode.The change in the reduction potential resulting from concentrationvariances may generally be calculated by the following equation:

E=E₀-R.T.In[M⁺],  (1)

[0033] wherein E generally represents the deposition potential of themetal, E₀ represents the standard deposition potential, R represents aconstant, T represents the temperature of the plating solution (which isgenerally at room temperature (15° C.-25° C.)), and M₊ represents theconcentration of the metal ions being plated in the plating solution.Therefore, since the standard deposition/reduction potential ofpalladium is substantially greater than the standard depositionpotential of copper, the reduction potential of palladium may be broughtcloser to the reduction potential of copper via manipulation of theprocessing parameters noted in equation (1). However, although equation(1) indicates that the reduction potentials for copper and palladium maybe brought closer in order to facilitate homogenous plating of acopper-palladium alloy, changes in ion concentrations alone generally donot result in large changes in the reduction potential of a metal.Additionally, conventional copper plating systems are generallyoptimized to achieve void free fill of high aspect ratio features, andtherefore, it is not desirable to modify the copper ion concentration inthe plating solution in order to achieve simultaneous copper andpalladium plating, as the copper plating characteristics may suffer fromthis modification. As such, another parameter that is adjusted in orderto obtain efficient and simultaneous plating of both copper andpalladium is the plating potential or current density applied to thesubstrate surface during the plating process.

[0034]FIG. 4 illustrates a current versus voltage schematic plot 400 fordeposition of copper and palladium individually. The standard reductionpotential for copper is 0.34 volts with respect to a standard hydrogenelectrode, while the standard reduction potential for palladium is 0.95volts with respect to a standard hydrogen electrode. In one embodiment,the measurements are taken at room temperature, which is about 20degrees Centigrade. At a cathodic potential of V₁, the amount ofpalladium deposition is represented by Pd₁ and the amount of copperdeposition is represented by Cu₁. At a cathodic potential of V₂, theamount of palladium deposition is represented by Pd₂ and the amount ofcopper deposition is represented by Cu₂. As the cathodic potential isincreased from V₁ to V₂, the amount of copper deposition increases fromCu₁ to Cu₂, while the amount of palladium deposition remains generallyabout the same, thereby decreasing the amount of palladium concentrationin the alloy. The concentration of Pd²⁺ ions in the electrolyte is smallenough such that the reduction of Pd²⁺ to Pd is mass-transfercontrolled. The same effect, to a limited extent, may be accomplished bydecreasing the concentration of palladium ions (Pd²⁺) in the platingsolution, while keeping the Cu²⁺ concentration constant. By decreasingthe concentration of palladium ions in the plating solution, the amountof palladium in the alloy is also decreased. Alternatively, althoughgenerally undesirable in conventional plating systems for the reasonsnoted above, the same effect maybe accomplished by increasing theconcentration of the copper ions (Cu²⁺) in the plating solution.Therefore, in view of the parameters that may be modified in order tofacilitate simultaneous copper-palladium deposition, embodiments of theinvention contemplate that the following processing parameters willallow for the formation of a substantially homogenous copper-palladiumalloy thin film in an electrochemical plating cell.

[0035] In accordance with an embodiment of the invention, a copperplating solution may be used to implement the formation of asubstantially homogenous copper-palladium alloy thin film in anelectrochemical plating cell. A conventional copper plating solution mayinclude, for example, a copper source, a halide source, and one or moreorganic additives configured to provide a control element over theplating characteristics of the plating solution. Copper platingsolutions are commercially available from companies such as Enthone andShipley, for example. The copper source for electrochemical platingsolutions may be a copper sulfate solution having a copper ionconcentration of between about 5 g/L and about 100 g/L. The platingsolution may additionally contain an acid, which may be at aconcentration of between about 5 g/L and about 200 g/L. The platingsolution may further contain halide ions, such as chloride, which may beat a concentration of between about 10 ppm and about 200 ppm. Exemplaryacids that may be used in plating solution include sulfuric acid,phosphoric acid, and/or derivatives thereof. In addition to using coppersulfate as the copper source, embodiments of the invention contemplatethat the plating solution may include other copper salts, such as copperfluoborate, copper gluconate, copper sulfamate, copper sulfonate, copperpyrophosphate, copper chloride, or copper cyanide, for example, as thecopper source. Embodiments of the invention, however, are not limited tothese parameters.

[0036] The plating solution additives, which may include levelers,inhibitors, suppressors, brighteners, accelerators, and/or otheradditives known in the art, are typically organic materials that adsorbonto the surface of the substrate being plated. Useful suppressorstypically include copolymers-ethylene oxide, propylene oxide,polyethers, such as polyethylene glycol (PEG), and/or other polymers,such as polyethylene-polypropylene oxides, which adsorb on the substratesurface, slowing down copper deposition in the adsorbed areas. Usefulaccelerators typically include sulfides or disulfides, such as bis(3-sulfopropyl) disulfide, MPSA, and SPS molecules, which compete withsuppressors for adsorption sites, accelerating copper deposition inadsorbed areas. Useful levelers typically include amines, thiadiazole,imidazole, and other nitrogen containing organics. Useful inhibitorstypically include sodium benzoate and sodium sulfite, which inhibit therate of copper deposition on the substrate.

[0037] During plating, the additives are generally consumed at thesubstrate surface. As such, plating systems generally include areplenishment mechanism configured to replace the additives consumed inthe plating process so that a relatively constant concentration of theadditives may be maintained in the plating solution. However, it isgenerally known that differences in diffusion rates of the variousadditives may result in varying concentrations of particular additivesat the top of a high aspect ratio feature compared to the bottom of thefeature, thereby setting up different plating rates at the top of thefeature versus the bottom of the feature. For example, suppressors maybe larger molecules that diffuse slower than accelerators, andtherefore, fewer suppressors may adsorb onto the bottom surface of ahigh aspect ratio feature than accelerators. As such, the bottom of thefeature may plate at a faster rate than the top of the feature, thusincreasing the fill rate of the feature. Therefore, an appropriatecomposition of additives in the plating solution is desired tofacilitate void-free fill of high aspect ratio features.

[0038] In order to simultaneously plate both copper and palladium,embodiments of the invention contemplate adding a source of palladiumions to the above noted copper plating solution. The source for thepalladium ions includes, for example, PdSO₄, PdCl₂, or other palladiumcontaining compounds acceptable to a copper electrochemical platingsolution. The concentration of the palladium ions in the platingsolution is generally between about 0.0005 M and about 0.1 M, while theconcentration of the copper ions in the plating solution is generallybetween about 0.1 M and about 1 M. In another embodiment of theinvention, the copper concentration in the plating solution may bebetween about 0.4 M and about 0.8 M. The plating current density appliedto the substrate during a copper-palladium electrodeposition processusing the copper-palladium plating solution described above may bebetween about 0.5 mA/cm² and about 80 mA/cm², for example, at a constantcurrent density. Alternatively, the plating current density may bevaried throughout the copper-palladium deposition process, i.e., thecurrent density may be stepped up, down, or alternated between lower andhigher current densities, i.e., pulsed, during a plating process. Forexample, the current density may be calculated to facilitatecopper-palladium deposition in an initial stage of filling a feature,and then the current density may be changed to facilitate a more copperheavy deposition once the feature is somewhat lined with acopper-palladium alloy at the interfaces. Additionally, the substratesupport member supporting the substrate during the copper-palladiumelectrodeposition process is generally rotated at between about 5 RPMand about 60 RPM, for example, while the flow rate of thecopper-palladium electroplating solution to the electroplating cell isup to about 7.5 GPM, for example. Embodiments of the inventioncontemplate that the plating cell is capable of providing generallyconstant hydrodynamics so that the flow of the plating solution acrossthe plating surface of the substrate is constant. In this manner, afresh supply of both copper and palladium ions is maintained at theplating surface, which is important to simultaneous plating operations,since one ion may generally deplete faster than another ion and causenon-uniformity (spatial non-homogenous alloys) in the alloy layer.

[0039] Once the homogenous copper-palladium layer is deposited, thelayer may be annealed. The annealing process may contribute to the grainsize determination, the grain distribution in the alloy, and thecrystalline structure of the alloy. Embodiments of the inventioncontemplate that an annealing process may be implemented to anneal thehomogenous copper-palladium alloy films, wherein the annealing processincludes exposing the film to a temperature of between about 200° C. andabout 400° C., for example. The exposure/annealing time for thecopper-palladium film may be between about 30 seconds and about 1 hour,depending upon the structure desired and the thermal budget availablefor the process. The resulting substantially homogenous copper-palladiumlayer will generally have a palladium concentration of up to about 2weight percent. More particularly, the homogenous copper-palladium alloyof the invention may have a palladium concentration of between about 0.2weight percent and about 1.5 weight percent, or between about 0.1 weightpercent and about 0.6 weight percent, for example.

[0040] Accordingly, various embodiments of the invention generallyprovide a method and apparatus for forming a substantially homogenouscopper-palladium alloy layer onto a semiconductor substrate, and inparticular, for filling high aspect ratio (4:1 or higher) features witha substantially homogenous copper-palladium alloy that has a largeconcentration of copper (above about 98.5 weight percent) and asubstantially smaller concentration of palladium (about 0.2 weightpercent to about 1.5 weight percent). The copper-palladium alloy, whichprovides enhanced electromigration and/or stress migration resistance inconductive features of semiconductor devices and prevents the formationof voids at the interfaces when high current is passed through theinterconnect, is generally formed onto the substrate and into thefeatures via an ECP process. Embodiments of the ECP process fordepositing the copper-palladium alloy generally include adding acalculated amount of palladium to a copper plating solution and applyinga calculated voltage to a substrate immersed in the plating solution.The calculated amount of palladium added to the plating solution and thecalculated voltage applied are specifically selected to provide for thedeposition of a substantially homogenous copper-palladium alloy.Additionally, embodiments of the invention are configured to plate thecopper-palladium alloy into very high aspect ratio features, e.g.,greater than 10:1, for narrow conductive structures, i.e., sub 0.10micron width features. The deposition of the copper-palladium alloy mayalso be accomplished by depositing a very thin copper-palladium layer ona PVD copper seed layer by an electroless deposition process followed byelectroplating the copper-palladium alloy in the plating solutiondescribed below.

[0041] Embodiments of the invention may be used in connection with adevice for measuring component quantities for use in apparatusimplementing multiple chemistries, as described in U.S. patentapplication Ser. No. ______ (AMAT/8465/CMP/ECP/RKK), entitled VOLUMEMEASUREMENT APPARATUS AND METHOD, by Balisky et al, filed Oct. 1, 2003,which is incorporated herein by reference. The measurement device may beused for measuring, adding, or mixing chemical components for variousplating processes, including direct plating on a barrier layer, alloyplating, alloy plating combined with convention metal plating, platingon a thin seed layer, optimized feature fill and bulk fill plating,plating multiple layers with minimal defects, or any other platingprocess where more than one chemistry may be beneficial to a platingprocess.

[0042] While the foregoing is directed to embodiments of the presentinvention, other and further embodiments of the invention may be devisedwithout departing from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

What is claimed is:
 1. A method for plating a homogenouscopper-palladium alloy, comprising: providing a plating solution to anelectrochemical plating cell, wherein the plating solution includes acopper ion source at a concentration of between about 0.1 M and about1.0 M and a palladium ion source at a concentration of between about0.0005 M and about 0.1 M; and supplying an electrical deposition bias toa plating surface, wherein the electrical deposition bias is configuredto simultaneously deposit copper ions and palladium ions onto theplating surface.
 2. The method of claim 1, wherein the palladium ionsource comprises at least one of PdSO₄ and PdCl₂.
 3. The method of claim1, wherein the concentration of the copper ion source is between about0.4 M and about 0.8 M.
 4. The method of claim 1, further comprisingplating the alloy on the plating surface, wherein the alloy comprisesabout 1.5 weight percent of palladium and about 98.5 weight percent ofcopper.
 5. The method of claim 4, wherein the palladium in the alloy isbetween about 0.2 weight percent and about 1.5 weight percent.
 6. Themethod of claim 4, further comprising annealing the alloy at atemperature of between about 200° C. and about 400° C. for a duration ofbetween about 30 seconds and about 60 minutes.
 7. The method of claim 1,wherein the electrical deposition bias has a current density of betweenabout 0.5 mA/cm² and about 80 mA/cm² over the plating surface.
 8. Themethod of claim 1, further comprising rotating the plating surfacebetween about 5 RPM and about 60 RPM while the electrical depositionbias is supplied to the plating surface.
 9. A method forelectrochemically plating an alloy onto a semiconductor substrate,comprising: providing a plating solution containing copper ions andpalladium ions; immersing a working surface of a substrate and an anodein the plating solution; and applying an electrical plating bias betweenthe anode and the working surface, wherein the electrical plating biasis configured to simultaneously plate copper and palladium out of theplating solution and onto the working surface.
 10. The method of claim9, wherein the electrical plating bias comprises a constant electricalbias.
 11. The method of claim 9, wherein the electrical plating biascomprises a pulsed bias, wherein a first portion of the pulse isconfigured to primarily plate copper and a second portion of the pulseis configured to primarily plate palladium.
 12. The method of claim 9,wherein the amount of copper ions in the plating solution is betweenabout 0.1 M and about 1.0 M and the amount of palladium ions in theplating solution is between about 0.0005 M and about 0.1 M.
 13. Themethod of claim 9, wherein the palladium ions comprise at least one ofPdSO₄ and PdCl₂.
 14. The method of claim 9, wherein the amount of copperions in the plating solution is between about 0.4 M and about 0.8 M. 15.The method of claim 9, further comprising plating the alloy onto theworking surface, wherein the alloy comprises about 1.5 weight percent ofpalladium and about 98.5 weight percent of copper.
 16. The method ofclaim 15, wherein the palladium in the alloy is between about 0.2 weightpercent and about 1.5 weight percent.
 17. The method of claim 15,further comprising annealing the alloy at a temperature of between about200° C. and about 400° C. for a duration of between about 30 seconds andabout 60 minutes.
 18. The method of claim 9, wherein the electricalplating bias has a current density of between about 0.5 mA/cm² and about80 mA/cm² over the working surface.
 19. The method of claim 9, furthercomprising rotating the substrate between about 5 RPM and about 60 RPMwhile applying the electrical plating bias between the anode and theworking surface.
 20. A plating solution for plating a copper palladiumalloy, comprising: a source of copper ions; a source of palladium ions;an acid at a concentration of between about 5 g/L about 200 g/L; and atleast one plating solution additive configured to control platingcharacteristics.
 21. The plating solution of claim 20, wherein thesource of palladium ions comprises at least one of PdSO₄ and PdCl₂. 22.The plating solution of claim 20, wherein a concentration of thepalladium ions in the plating solution is between about 0.0005 M andabout 0.1 M.
 23. The plating solution of claim 20, wherein aconcentration of the copper ions in the plating solution is betweenabout 0.1 M and about 1 M.
 24. The plating solution of claim 20, whereina concentration of the copper ions in the plating solution is betweenabout 0.4 M and about 0.8 M.
 25. The plating solution of claim 20,wherein the acid comprises at least one of sulfuric acid and phosphoricacid.
 26. An electrochemical plating cell configured to plate ahomogenous copper-palladium alloy into features of a semiconductordevice, comprising: a substrate support member having a substantiallyplanar lower surface configured to engage a non-production side of asubstrate; an annular insulative cathode contact ring having a pluralityof conductive substrate biasing members formed therein, wherein each ofthe plurality of conductive biasing members is configured toelectrically engage a plating surface of a substrate; a plating cellcontainer configured to hold a volume of electrochemical platingsolution; a power supply in electrical communication with the pluralityof conductive members and being configured to apply a plating bias tothe plating surface; an anode positioned in the plating cell containerin a position where the anode is immersed in the electrochemical platingsolution; and a process controller programmed to maintain a copper ionconcentration between about 0.1 M and about 1.0 M and a palladium ionconcentration between about 0.0005 M and about 0.1 M in theelectrochemical plating solution.
 27. The electrochemical plating cellof claim 26, wherein the process controller is further configured tomaintain the plating bias at a current density of between about 0.5mA/cm² and about 80 mA/cm².